In order for an integrated circuit to operate properly, some elements within the integrated circuit must be synchronized. One common method of synchronizing elements of an integrated circuit is to use a clock signal that is routed to the elements. This clock signal is generated using a clock signal generator and then distributed to the various elements through a clock signal distribution network.
The physical clock signal distribution network is made up of conductive lines formed on the integrated circuit and interweaved among the functional blocks and the power grid. As such, the physical design of a clock signal distribution network is heavily dependent upon the placement and other features located on the die.
However, this physical distribution network has some serious drawbacks. The first such drawback is timing skew. This occurs when clocking signal delays to different parts of the integrated circuit are not equal, thereby causing the various elements to be out of synch. Timing skew can be caused by electromagnetic propagation delays, buffer delays in the distribution network, and resistive-capacitive delays associated with the distribution lines themselves. This problem is further exacerbated by the routing constraints of placing the lines between, around, and among the other functional elements of the integrated circuit.
Another problem is corruption of the clock signal due to coupling from the signal network and/or the power network. When the clock distribution network is integrated among the power nets and even among themselves, the signals within each line will interfere with the signals in the other lines, and cause some corruption of the clock signal. Such a problem is normally solved by increasing the distance between the coupling lines, but, in a single, closely packed integrated circuit, this solution is not feasible because it incurs prohibitive area penalty.
Yet another problem involves a simple matter of efficiency. Because of the placement of the clocks and signals, the clock distribution network must be routed around the functional elements and power networks of the rest of the die. This design is simply inefficient because the distribution network can rarely be run in a straight line between the clock signal generator and the element to be controlled.
Accordingly, what is needed is a clock distribution network that is designed to improve clock purity and prevent skew problems across a die while improving die area utilization in clocked integrated circuits.